1. Field of the Invention
The present invention relates generally to a packaging substrate structure with a semiconductor chip embedded therein, and more particularly, to a packaging substrate structure with a semiconductor chip embedded therein having a buffer layer.
2. Description of Related Art
With the rapid development of semiconductor package technologies, there have been developed various kinds of packages for semiconductor devices, which mainly involves mounting a semiconductor chip to a packaging substrate, electrically connecting the semiconductor chip to the packaging substrate and encapsulating the whole structure. Therein, BGA (Ball Grid Array) package technology is a developed package technology, which is characterized in that one side of a packaging substrate is mounted with a semiconductor chip and the other side of the packaging substrate is mounted with a plurality of solder balls arranged in an array such that more I/O connections can be accommodated in a unit area of the chip carrier. Further, the whole package can be electrically connected to a printing circuit board through the solder balls.
Although such a structure achieves a high pin count, as the semiconductor chip is electrically connected to the substrate by wire bonding or flip chip, the relatively long conductive wire connection paths increase impedance during high-frequency or high-speed operation, thus preventing electrical performance of the package from being improved.
Accordingly, semiconductor chip embedding structures with semiconductor chips embedded in circuit boards are developed to shorten an electrical conduction path, decrease signal loss and distortion, and improve high-speed operation.
FIGS. 1A to 1D show a fabrication method of a conventional semiconductor chip embedding structure. First, providing a carrier board 10 having a first surface 10a and a second surface 10b opposing the first surface 10a. The carrier board 10 is formed with at least a through cavity 100 penetrating the first surface 10a and the second surface 10b, and a releasing film 101 is formed on the second surface 10b, as shown in FIG. 1A; then, a semiconductor chip 11 is received in the through cavity 100 of the carrier board 10, wherein the semiconductor chip 11 has an active surface 11a and an inactive surface 11b opposing the active surface 11a, the semiconductor chip 11 is mounted on the surface of the releasing film 101 in the through cavity 100 through the inactive surface 11b, the active surface 11a of the semiconductor chip 11 has a plurality of electrode pads 112, a passivation layer 113 is formed on the active surface 11a with the electrode pads 112 exposed therefrom, and metal pads 114 are formed on surfaces of the electrode pads 112, as shown in FIG. 1B; subsequently, a dielectric layer 12 is formed on the first surface 10a of the carrier board 10 and the active surface 11a of the semiconductor chip 11. The dielectric layer 12 is also formed in the spacing between the through cavity 100 and the semiconductor chip 11 so as to fix the semiconductor chip 11 in the through 100. The dielectric layer 12 has a plurality of openings 120 to expose the electrode pads 112 of the semiconductor chip 11, as shown in FIG. 1C; finally, a circuit layer 13 is formed on the dielectric layer 12, conductive structures 131 are formed in the openings 120 of the dielectric layer 12 to be electrically connected to the metal pads 114 of the semiconductor chip 11, and the releasing film 101 is removed, as shown in FIG. 1D.
The semiconductor chip embedding structure fabricated by the aforesaid process shortens the electrical conduction path, decreases signal loss and distortion, and improves high-frequency operation.
However, as there exists a big difference between the CTE (Coefficients of Thermal Expansion) of the semiconductor chip 11 (about 3 ppm/° C.) and the CTE of the dielectric layer 12 (about 50 ppm/° C.), thermal stress is generated on the interface of the two materials in the process, resulting in warpage or delamination, thereby adversely affecting the quality of the semiconductor chip embedding structure, and even ruining the embedding structure or semiconductor chip.
Therefore, there exists a strong need in the art for a semiconductor chip embedding structure to overcome the drawbacks of the aforesaid conventional technology.